CMOS (Complementary Metal Oxide Semiconductor) image sensors (CIS) are characterized as compared with CCD (Charge Coupled Device) image sensors in that it is possible to relatively freely set a readout address.
For example, a widely used sensor thereof is a sensor that has not only a function of readout of all the pixels of the sensor but also functions of “addition” which simultaneously reads out signals of a plurality of pixels, “thinning-out” which intermittently reads out the signals while skipping rows or columns, “cutout” which reads out only from some pixels, and the like.
Sometimes “addition”, “thinning-out” and “cutout” may be simultaneously performed.
In the sensor having the functions of “thinning-out”, “addition”, and “cutout”, the readout and shutter operation becomes complicated. Hence, inmost cases, for row selection, not shift registers but decoders are used.
In image sensors, there is a known phenomenon called blooming in which signal charge overflows from saturated photodiodes (hereinafter referred to as PDs) to adjacent PDs and thereby the signal amount changes.
In other words, the blooming is defined as a phenomenon in which electric charge is accumulated in photodiodes until it becomes saturated and the electric charge overflows from the photodiodes to adjacent pixels when light incidence is further continued.
Modes, in which deterioration in image quality is caused by the blooming, are roughly classified into two types. In a thinning-out operation of a CMOS sensor as one mode thereof, extra electric charge of pixels, which do not contribute to the output signals of the sensor, is collected, and this electric charge overflows in the pixels which contribute to the sensor output signals. In this case, image quality significantly deteriorates.
As a countermeasure for the blooming in the thinning-out mode, for example, there has been proposed a method of discharging the extra electric charge by generating an electronic shutter with a circuit configuration in which a decoder and a 2-bit memory are disposed in each row of the vertical selection circuit (refer to JP-A-2008-288903).
Further, there has been proposed a specific method of controlling addresses of the decoders (refer to JP-A-2008-288904).